| A one-shot configurable-cache tuner for improved energy and performance A Gordon-Ross, P Viana, F Vahid, W Najjar, E Barros 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 50 | 2007 |
| Configurable cache subsetting for fast cache tuning P Viana, A Gordon-Ross, E Keogh, E Barros, F Vahid Proceedings of the 43rd annual Design Automation Conference, 695-700, 2006 | 36 | 2006 |
| Exploring memory hierarchy with ArchC P Viana, E Barros, S Rigo, R Azevedo, G Araújo Proceedings. 15th Symposium on Computer Architecture and High Performance …, 2003 | 34 | 2003 |
| A table-based method for single-pass cache optimization P Viana, A Gordon-Ross, E Barros, F Vahid Proceedings of the 18th ACM Great Lakes symposium on VLSI, 71-76, 2008 | 26 | 2008 |
| Cache-analyzer: design space evaluation of configurable-caches in a single-pass A Silva, G Esmeraldo, E Barros, P Viana 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP'07), 3-9, 2007 | 14 | 2007 |
| Modeling and simulating memory hierarchies in a platform-based design methodology P Viana, E Barros, S Rigo, R Azevedo, G Araújo Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 11 | 2004 |
| Minimum effort design space subsetting for configurable caches MH Alsafrjalani, AG Ross, P Viana 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing …, 2014 | 7 | 2014 |
| Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption AG Silva Filho, P Viana, E Barros, ME Lima 2006 18th International Symposium on Computer Architecture and High …, 2006 | 2 | 2006 |
| Turismo, cultura, patrimônio cultural e desenvolvimento em Curuçá (Pará, Brasil): uma relação possível? ACR Silva, A Anschau, PVV Pereira, LTL Simonian Amazonia Investiga 8 (18), 243-260, 2019 | 1 | 2019 |
| Avaliaςão do Consumo de Energia e Tempo de Vida de Redes de Sensores sem Fio Comerciais CV da Silva, AC Frery, P Viana Mecánica Computacional 29 (26), 2663-2672, 2010 | 1 | 2010 |
| Configurable Cache Tuning: A Methodology to Explore Memory Hierarchy Architectures for Embedded Systems P Viana LAP Lambert Academic Publishing, 2009 | | 2009 |
| SBESC 2011 A Silva-Filho, A Trevisan, AA Fröhlich, CE Pereira, C Zeferino, C Araújo, ... | | |
| Technical Program Committee EUC 2014 F Borlenghi, M Glass, G Gogniat, F UEB, F Hannig, S Isaza, D Sciuto, ... | | |
| SBESC 2012 R Azevedo, S Johann Filho, J Monteiro, A Tavares, A Rettberg, C Galuzzi, ... | | |
| APSEC 2010 VS Agneeswaran, A Babar, C Babu, G Bae, JH Bae, F Brosch, B Bui, ... | | |
