Marcelo Cintra
Marcelo Cintra
Head of Scientific Computing at CAESAR and Honorary Professor at University of Edinburgh
Verified email at caesar.de
Title
Cited by
Cited by
Year
Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors
M Cintra, JF Martínez, J Torrellas
International Symposium on Computer Architecture (ISCA), 13-24, 2000
2762000
Toward Efficient and Robust Software Speculative Parallelization on Multiprocessors
M Cintra, DR Llanos
International Symposium on Principles and Practice of Parallel Programming …, 2003
1612003
Generating Code for Holistic Query Evaluation
K Krikellas, SD Viglas, M Cintra
International Conference on Data Engineering (ICDE), 613-624, 2010
1472010
Rewind: Recovery write-ahead system for in-memory non-volatile data-structures
A Chatzistergiou, M Cintra, SD Viglas
Proceedings of the VLDB Endowment 8 (5), 497-508, 2015
1362015
Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
M Cintra, J Torrellas
International Symposium on High-Performance Computer Architecture (HPCA), 43-54, 2002
1042002
Efficient persist barriers for multicores
A Joshi, V Nagarajan, M Cintra, S Viglas
International Symposium on Microarchitecture (MICRO), 660-671, 2015
992015
Design Space Exploration of a Software Speculative Parallelization Scheme
M Cintra, DR Llanos
IEEE Transactions on Parallel and Distributed Systems (TPDS) 16 (6), 562-576, 2005
942005
ATOM: Atomic durability in non-volatile memory through hardware logging
A Joshi, V Nagarajan, S Viglas, M Cintra
International Symposium on High Performance Computer Architecture (HPCA …, 2017
842017
Using Predictive Modeling for Cross-Program Design Space Exploration in Multicore Systems
S Khan, P Xekalakis, J Cavazos, M Cintra
International Conference on Parallel Architecture and Compilation Techniques …, 2007
802007
An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
C Fensch, M Cintra
International Symposium on High Performance Computer Architecture (HPCA …, 2008
752008
Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer
N Ioannou, M Kauschke, M Gries, M Cintra
International Conference on Parallel Architectures and Compilation …, 2011
632011
Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching
P Diaz, M Cintra
International Symposium on Computer Architecture (ISCA), 81-92, 2009
562009
A Machine Learning-Based Approach for Thread Mapping on Transactional Memory Applications
M Castro, LFW Góes, CP Ribeiro, M Cole, M Cintra, JF Méhaut
International Conference on High Performance Computing (HiPC), 1-10, 2011
512011
A Machine Learning-Based Approach for Thread Mapping on Transactional Memory Applications
L Goes, CP Ribeiro, M Cintra, JF Mehaut
International Conference on High Performance Computing (HiPC), 2011
51*2011
Combining Thread Level Speculation, Helper Threads and Runahead Execution
P Xekalakis, N Ioannou, M Cintra
International Conference on Supercomputing (ICS), 410-420, 2009
512009
Software-Based Cache Coherence with Hardware-Assisted Selective Self Invalidations Using Bloom Filters
T Ashby, P Diaz, M Cintra
IEEE Transactions on Computers (TC) 60 (4), 472-483, 2011
482011
A compiler Cost Model for Speculative Parallelization
J Dou, M Cintra
ACM Transactions on Architecture and Code Optimization (TACO) 4 (2), 12, 2007
462007
DHTM: Durable hardware transactional memory
A Joshi, V Nagarajan, M Cintra, S Viglas
International Symposium on Computer Architecture (ISCA), 452-465, 2018
352018
Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization
J Dou, M Cintra
International Conference on Parallel Architectures and Compilation …, 2004
342004
DRIFT: Decoupled compileR-based Instruction-level Fault-Tolerance⋆
K Mitropoulou, V Porpodas, M Cintra
International Workshop on Languages and Compilers for Parallel Computing (LCPC), 2013
242013
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Articles 1–20