| Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits AP Shah, V Neema, S Daulatabad, P Singh Microsystem Technologies 25, 1639-1652, 2019 | 21 | 2019 |
| Effect of process, voltage and temperature (PVT) variations In LECTOR-B (leakage reduction technique) at 70 nm technology node AP Shah, V Neema, S Daulatabad 2015 International Conference on Computer, Communication and Control (IC4), 1-6, 2015 | 13 | 2015 |
| 8-bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node S Daulatabad, V Neema, AP Shah, P Singh Procedia Computer Science 79, 589-596, 2016 | 12 | 2016 |
| DOIND: a technique for leakage reduction in nanoscale domino logic circuits AP Shah, V Neema, S Daulatabad Journal of Semiconductors 37 (5), 055001, 2016 | 9 | 2016 |
| PVT variations aware low leakage DOIND approach for nanoscale domino logic circuits AP Shah, V Neema, S Daulatabad 2015 IEEE Power, Communication and Information Technology Conference (PCITC …, 2015 | 8 | 2015 |
| Subthreshold circuit designing and implementation of finite field multiplier for cryptography application P Singh, V Neema, S Daulatabad, AP Shah Procedia Computer Science 79, 597-602, 2016 | 5 | 2016 |
| Comparative study of Area, Delay and Power Dissipation for LECTOR and INDEP (Leakage control techniques) at 70 nm technology node AP Shah, V Neema, S Daulatabad 2015 IEEE International Advance Computing Conference (IACC), 513-518, 2015 | 5 | 2015 |
| A novel leakage reduction DOIND approach for nanoscale domino logic circuits AP Shah, V Neema, S Daulatabad 2015 Eighth International Conference on Contemporary Computing (IC3), 434-438, 2015 | 4 | 2015 |
| DYNOC: an energy efficient novel approach for nanoscale domino logic circuits AP Shah, V Neema, S Daulatabad, P Singh 3rd International Conference on Microelectronics, Circuits & Systems, Micro …, 2016 | 2 | 2016 |
| An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve Multifold Transient Frequency Enhancement S Daulatabad, PS Swain, H Gossner, MS Baghini IEEE Transactions on Electron Devices 69 (9), 5074-5081, 2022 | | 2022 |
| Comparative analysis of DOIND approach with and without body biasing for leakage reduction in domino logic circuits AP Shah, V Neema, S Daulatabad 2015 International Conference on Signal Processing, Computing and Control …, 2015 | | 2015 |
Ambika Prasad ShahAssistant Professor, Electrical Engineering Department, Indian Institute of Technology JammuVerified email at iitjammu.ac.in
