| A modular digital VLSI flow for high-productivity SoC design B Khailany, E Khmer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 73 | 2018 |
| Design and implementation of an" approximate" communication system for wireless media applications S Sen, S Gilani, S Srinath, S Schmitt, S Banerjee Proceedings of the ACM SIGCOMM 2010 Conference, 15-26, 2010 | 57 | 2010 |
| Microarchitectural mechanisms to exploit value structure in SIMT architectures J Kim, C Torng, S Srinath, D Lockhart, C Batten Proceedings of the 40th Annual International Symposium on Computer …, 2013 | 45 | 2013 |
| An architectural framework for accelerating dynamic parallel algorithms on reconfigurable hardware T Chen, S Srinath, C Batten, GE Suh 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 38 | 2018 |
| Dynamic hazard resolution for pipelining irregular loops in high-level synthesis S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 38 | 2017 |
| Architectural specialization for inter-iteration loop dependence patterns S Srinath, B Ilbeyi, M Tan, G Liu, Z Zhang, C Batten 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 583-595, 2014 | 38 | 2014 |
| Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks S Srinath, K Compton Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010 | 36 | 2010 |
| Effective processor verification with logic fuzzer enhanced co-simulation N Kabylkas, T Thorn, S Srinath, P Xekalakis, J Renau MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 17 | 2021 |
| Improving high-level synthesis with decoupled data structure optimization R Zhao, G Liu, S Srinath, C Batten, Z Zhang Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 17 | 2016 |
| Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs J Kim, S Jiang, C Torng, M Wang, S Srinath, B Ilbeyi, K Al-Hawaj, C Batten Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 14 | 2017 |
| Accelerating a PARSEC benchmark using portable subword SIMD S Ghose, S Srinath, J Tse CS 5220: Final Project Report. Sch. of Elec. and Comp. Eng., Cornell Eng, 2011 | 6 | 2011 |
| Rough neuron based neural classifier A Kothari, A Keskar, R Chalasani, S Srinath 2008 First International Conference on Emerging Trends in Engineering and …, 2008 | 6 | 2008 |
| Design and implementation of an “approximate” communication system for wireless media applications S Sen, T Zhang, S Gilani, S Srinath, S Banerjee, S Addepalli IEEE/ACM Transactions on Networking 21 (4), 1035-1048, 2012 | 4 | 2012 |
| Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. C Torng, M Wang, B Sudheendra, N Murali, S Jayasuriya, S Srinath, ... Hot Chips Symposium, 1, 2016 | 3 | 2016 |
| Lane-Based Hardware Specialization for Loop-and Fork-Join-Centric Parallelization and Scheduling Strategies S Srinath Cornell University, 2018 | 2 | 2018 |
| Synchronous microthreading DB Sheffield, E Boleyn, J Pearce, S Pediaditaki, J Cook, S Srinath, ... US Patent App. 17/712,130, 2023 | | 2023 |
| Synchronous microthreading DB Sheffield, E Boleyn, J Pearce, S Pediaditaki, J Cook, S Srinath, ... US Patent App. 17/712,124, 2023 | | 2023 |
| Synchronous microthreading S Srinath, J Pearce, DB Sheffield, CK Liang, J Cook US Patent App. 17/712,120, 2023 | | 2023 |
| Synchronous microthreading DB Sheffield, E Boleyn, J Pearce, S Pediaditaki, J Cook, S Srinath, ... US Patent App. 17/712,126, 2023 | | 2023 |
| Synchronous microthreading DB Sheffield, E Boleyn, J Pearce, S Pediaditaki, J Cook, S Srinath, ... US Patent App. 17/712,129, 2023 | | 2023 |
Christopher BattenCornell UniversityVerified email at cornell.edu
