Jose Monteiro
TitleCited byYear
Precomputation-based sequential logic optimization for low power
M Alidina, J Monteiro, S Devadas, A Ghosh, M Papaefthymiou
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (4), 426-436, 1994
4351994
Precomputation-based sequential logic optimization for low power
M Alidina, J Monteiro, S Devadas, A Ghosh, M Papefthymiou
Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994
4351994
Retiming sequential circuits for low power
J Monteiro, S Devadas, A Ghosh
International journal of high speed electronics and systems 7 (02), 323-340, 1996
2511996
Power estimation methods for sequential logic circuits
CY Tsui, J Monteiro, M Pedram, S Devadas, AM Despain, B Lin
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (3), 404-416, 1995
1811995
Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications
L Aksoy, E Da Costa, P Flores, J Monteiro
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
1552008
A methodology for efficient estimation of switching activity in sequential logic circuits
J Monteiro, S Devadas, B Lin
31st Design Automation Conference, 12-17, 1994
1531994
Scheduling techniques to enable power management
J Monteiro, S Devadas, P Ashar, A Mauskar
33rd Design Automation Conference Proceedings, 1996, 349-352, 1996
1391996
Finite state machine decomposition for low power
JC Monteiro, AL Oliveira
Proceedings of the 35th annual Design Automation Conference, 758-763, 1998
1001998
Estimation of average switching activity in combinational logic circuits using symbolic simulation
J Monteiro, S Devadas, A Ghosh, K Keutzer, J White
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1997
1001997
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
P Flores, J Monteiro, E Costa
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
792005
Switching activity estimation using limited depth reconvergent path analysis
JC Costa, JC Monteiro, S Devadas
Proceedings of 1997 International Symposium on Low Power Electronics and …, 1997
781997
Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation
P Flores, J Costa, H Neto, J Monteiro, J Marques-Silva
Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999
581999
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
J Monteiro, S Devadas
Springer Science & Business Media, 2012
482012
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
J Monteiro, S Devadas
Proceedings of the 1995 international symposium on Low power design, 33-38, 1995
481995
Design of digit-serial FIR filters: Algorithms, architectures, and a CAD tool
L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro
IEEE transactions on very large Scale integration (VLSI) systems 21 (3), 498-511, 2012
462012
Optimization of combinational and sequential logic circuits for low power using precomputation
J Monteiro, J Rinderknecht, S Devadas, A Ghosh
Proceedings Sixteenth Conference on Advanced Research in VLSI, 430-444, 1995
461995
Optimization of area in digital FIR filters using gate-level metrics
L Aksoy, E Costa, P Flores, J Monteiro
2007 44th ACM/IEEE Design Automation Conference, 420-423, 2007
442007
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11 …
J Monteiro, R van Leuken
Springer Science & Business Media, 2010
422010
A new architecture for signed radix-2/sup m/pure array multipliers
E Costa, S Bampi, J Monteiro
Proceedings. IEEE International Conference on Computer Design: VLSI in …, 2002
332002
Implicit FSM decomposition applied to low-power design
JC Monteiro, AL Oliveira
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (5), 560-565, 2002
322002
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