Muhammad Khellah
Muhammad Khellah
Verified email at intel.com
TitleCited byYear
Trading off cache capacity for reliability to enable low voltage operation
C Wilkerson, H Gao, AR Alameldeen, Z Chishti, M Khellah, SL Lu
ACM SIGARCH computer architecture news 36 (3), 203-214, 2008
2892008
A 45 nm resilient microprocessor core for dynamic variation tolerance
KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ...
IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010
2602010
Floating-body dynamic random access memory and method of fabrication in tri-gate technology
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,098,507, 2006
1652006
Floating-body memory cell write
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,061,806, 2006
1242006
Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs
M Khellah, Y Ye, N Kim, D Somasekhar, G Pandya, A Farhang, K Zhang, ...
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 9-10, 2006
1222006
Floating-body DRAM using write word line for increased retention time
S Tang, A Keshavarzi, D Somasekhar, F Paillet, M Khellah, Y Ye, V De
US Patent 6,903,984, 2005
1212005
Floating-body dynamic random access memory with purge line
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,002,842, 2006
1112006
Method and apparatus to generate a reference value in a memory array
D Somasekhar, Y Ye, MM Khellah, F Paillet, SH Tang, A Keshavarzi, ...
US Patent 6,952,376, 2005
1102005
Method for making memory cell without halo implant
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,001,811, 2006
1082006
Asymmetric memory cell
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 6,992,339, 2006
1082006
Purge-based floating body memory
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,230,846, 2007
1062007
Floating-body DRAM with two-phase write
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,072,205, 2006
1052006
OTP antifuse cell and cell array
F Paillet, A Keshavarzi, MM Khellah, D Somasekhar, Y Ye, SH Tang, ...
US Patent 7,102,951, 2006
1042006
Multi-phase 1 GHz voltage doubler charge pump in 32 nm logic process
D Somasekhar, B Srinivasan, G Pandya, F Hamzaoglu, M Khellah, ...
IEEE Journal of Solid-State Circuits 45 (4), 751-758, 2010
1012010
Network access method and mobile communication terminal
H Liu
US Patent 10,117,163, 2018
872018
Bi-directional multi-mode charge pump
J Kulkarni, S Yong, PA MEINERZHAGEN, MM Khellah
US Patent 10,014,767, 2018
852018
Accurate estimation of SRAM dynamic stability
DE Khalil, M Khellah, NS Kim, Y Ismail, T Karnik, VK De
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (12 …, 2008
812008
A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS
R Jain, BM Geuskens, ST Kim, MM Khellah, J Kulkarni, JW Tschanz, V De
IEEE Journal of Solid-State Circuits 49 (4), 917-927, 2014
802014
2 GHz 2 Mb 2T gain cell memory macro with 128 GBytes/sec bandwidth in a 65 nm logic process technology
D Somasekhar, Y Ye, P Aseron, SL Lu, MM Khellah, J Howard, G Ruhl, ...
IEEE Journal of Solid-State Circuits 44 (1), 174-185, 2008
782008
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance
J Tschanz, K Bowman, SL Lu, P Aseron, M Khellah, A Raychowdhury, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 282-283, 2010
752010
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