Naresh Shanbhag
Naresh Shanbhag
Professor of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
Verified email at illinois.edu - Homepage
TitleCited byYear
High-throughput LDPC decoders
MM Mansour, NR Shanbhag
IEEE transactions on very large scale integration (VLSI) Systems 11 (6), 976-996, 2003
6692003
High-speed architectures for Reed-Solomon decoders
DV Sarwate, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (5), 641-655, 2001
3972001
Soft-error-rate-analysis (SERA) methodology
M Zhang, NR Shanbhag
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
2992006
A 640-Mb/s 2048-bit programmable LDPC decoder chip
MM Mansour, NR Shanbhag
IEEE Journal of Solid-State Circuits 41 (3), 684-698, 2006
2962006
Soft digital signal processing
R Hegde, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (6), 813-823, 2001
2932001
A coding framework for low-power address and data busses
S Ramprasad, NR Shanbhag, IN Hajj
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (2), 212-221, 1999
2681999
Low-power VLSI decoder architectures for LDPC codes
MM Mansour, NR Shanbhag
Proceedings of the International Symposium on Low Power Electronics and …, 2002
2522002
Energy-efficient signal processing via algorithmic noise-tolerance
R Hegde, NR Shanbhag
Proceedings. 1999 International Symposium on Low Power Electronics and …, 1999
2431999
Sequential element design with built-in soft error resilience
M Zhang, S Mitra, TM Mak, N Seifert, NJ Wang, Q Shi, KS Kim, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (12 …, 2006
2322006
Coding for system-on-chip networks: a unified framework
SR Sridhara, NR Shanbhag
IEEE transactions on very large scale integration (VLSI) systems 13 (6), 655-667, 2005
2182005
Coupling-driven signal encoding scheme for low-power interface design
KW Kim, KH Baek, N Shanbhag, CL Liu, SM Kang
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided …, 2000
2012000
Reliable low-power digital signal processing via reduced precision redundancy
B Shim, SR Sridhara, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (5), 497-510, 2004
1962004
Stochastic computation
NR Shanbhag, RA Abdallah, R Kumar, DL Jones
Design Automation Conference, 859-864, 2010
1762010
Energy-efficient soft error-tolerant digital signal processing
B Shim, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (4), 336-348, 2006
1572006
Toward achieving energy efficiency in presence of deep submicron noise
R Hegde, NR Shanbhag
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 379-391, 2000
1572000
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew
JE Jaussi, G Balamurugan, DR Johnson, B Casper, A Martin, J Kennedy, ...
IEEE Journal of Solid-State Circuits 40 (1), 80-88, 2005
1342005
Area and energy-efficient crosstalk avoidance codes for on-chip buses
SR Sridhara, A Ahmed, NR Shanbhag
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
1122004
Pipelined adaptive digital filters
NR Shanbhag, KK Parhi
Springer Science & Business Media, 2012
1032012
Coding for reliable on-chip buses: A class of fundamental bounds and practical codes
SR Sridhara, NR Shanbhag
IEEE Trans. on CAD of Integrated Circuits and Systems 26 (5), 977-982, 2007
972007
Turbo decoder architectures for low-density parity-check codes
MM Mansour, NR Shanbhag
Global Telecommunications Conference, 2002. GLOBECOM'02. IEEE 2, 1383-1388, 2002
912002
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Articles 1–20