Guillermo PayŠ-VayŠ
Guillermo PayŠ-VayŠ
Junior Professor, Institute of Microelectronic Systems, Leibniz Universitšt Hannover, Germany
Verified email at ims.uni-hannover.de - Homepage
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Year
VLIW architecture optimization for an efficient computation of stereoscopic video applications
G PayŠ-VayŠ, J Martin-Langerwerf, C Banz, F Giesemann, P Pirsch, ...
The 2010 International Conference on Green Circuits and Systems, 457-462, 2010
162010
Performance monitoring for automatic speech recognition in noisy multi-channel environments
BT Meyer, SH Mallidi, AMC Martinez, G PayŠ-VayŠ, H Kayser, ...
2016 IEEE Spoken Language Technology Workshop (SLT), 50-56, 2016
132016
2D-DCT on FPGA by polynomial transformation in two-dimensions
AM PatiŮo, MM Peirů, F Ballester, G Paya
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No†…, 2004
122004
A fair comparison of adders in stochastic regime
A Najafi, M WeiŖbrich, GP VayŠ, A Garcia-Ortiz
2017 27th International Symposium on Power and Timing Modeling, Optimization†…, 2017
102017
A multi-shared register file structure for VLIW processors
G PayŠ-VayŠ, J MartŪn-Langerwerf, P Pirsch
Journal of Signal Processing Systems 58 (2), 215-231, 2010
102010
Design space exploration of media processors: A parameterized scheduler
G Paya-Vaya, J Martin-Langerwerf, P Taptimthong, P Pirsch
2007 international conference on embedded computer systems: Architectures†…, 2007
102007
Design space exploration of media processors: A generic VLIW architecture and a parameterized scheduler
G PayŠ-VayŠ, J MartŪn-Langerwerf, P Taptimthong, P Pirsch
International Conference on Architecture of Computing Systems, 254-267, 2007
102007
Customizing a vliw-simd application-specific instruction-set processor for hearing aid devices
J Hartig, L Gerlach, G PayŠ-VayŠ, H Blume
2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014
92014
Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor architecture
G PayŠ-VayŠ, R Burg, H Blume
Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 26, 2012
92012
Design and analysis of a generic VLIW processor for multimedia applications
G PayŠ-VayŠ
Diss. Institute of Microelectronic Systems, Leibniz Universitšt Hannover, 2011
92011
Implementing a Margolus neighborhood cellular automata on a FPGA
J Cerda, R Gadea, G Paya
International Work-Conference on Artificial Neural Networks, 121-128, 2003
92003
Coherent design of hybrid approximate adders: Unified design framework and metrics
A Najafi, M WeiŖbrich, G Paya-Vaya, A Garcia-Ortiz
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4†…, 2018
82018
An area efficient real-and complex-valued multiply-accumulate SIMD unit for digital signal processors
L Gerlach, G PayŠ-VayŠ, H Blume
2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015
82015
ASEV—Automatic situation assessment for event-driven video analysis
M Fenzi, J Ostermann, N Mentzer, G PayŠ-VayŠ, H Blume, TN Nguyen, ...
2014 11th IEEE international conference on advanced video and signal based†…, 2014
82014
Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms
OJ Arndt, D Becker, F Giesemann, G PayŠ-VayŠ, C Bartels, H Blume
2014 International Conference on Embedded Computer Systems: Architectures†…, 2014
82014
Optimizing VLIW-SIMD processor architectures for FPGA implementation
S Nolting, G PayŠ-VayŠ, H Blume
Proceedings of the ICT. OPEN 2011, 2011
82011
Instruction merging to increase parallelism in VLIW architectures
G PayŠ-VayŠ, J MartŪn-Langerwerf, F Giesemann, H Blume, P Pirsch
2009 International Symposium on System-on-Chip, 143-146, 2009
82009
An enhanced dma controller in simd processors for video applications
G PayŠ-VayŠ, J MartŪn-Langerwerf, S Moch, P Pirsch
International Conference on Architecture of Computing Systems, 159-170, 2009
82009
RAPANUI: Rapid prototyping for media processor architecture exploration
GP VayŠ, JM Langerwerf, P Pirsch
International Workshop on Embedded Computer Systems, 32-40, 2005
82005
FLINT: Layout-oriented FPGA-based methodology for fault tolerant ASIC design
R Nowosielski, L Gerlach, S Bieband, G PayŠ-VayŠ, H Blume
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 297-300, 2015
72015
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