| Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology V Seshadri, D Lee, T Mullins, H Hassan, A Boroumand, J Kim, MA Kozuch, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 466 | 2017 |
| Google workloads for consumer devices: Mitigating data movement bottlenecks A Boroumand, S Ghose, Y Kim, R Ausavarungnirun, E Shiu, R Thakur, ... Proceedings of the Twenty-Third International Conference on Architectural …, 2018 | 287 | 2018 |
| Fast bulk bitwise AND and OR in DRAM V Seshadri, K Hsieh, A Boroum, D Lee, MA Kozuch, O Mutlu, PB Gibbons, ... IEEE Computer Architecture Letters 14 (2), 127-131, 2015 | 207 | 2015 |
| LazyPIM: An efficient cache coherence mechanism for processing-in-memory A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, K Hsieh, KT Malladi, ... IEEE Computer Architecture Letters 16 (1), 46-50, 2016 | 190 | 2016 |
| Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation K Hsieh, S Khan, N Vijaykumar, KK Chang, A Boroumand, S Ghose, ... 2016 IEEE 34th International Conference on Computer Design (ICCD), 25-32, 2016 | 185 | 2016 |
| Gather-scatter DRAM: In-DRAM address translation to improve the spatial locality of non-unit strided accesses V Seshadri, T Mullins, A Boroumand, O Mutlu, PB Gibbons, MA Kozuch, ... Proceedings of the 48th International Symposium on Microarchitecture, 267-280, 2015 | 142 | 2015 |
| Processing-in-memory: A workload-driven perspective S Ghose, A Boroumand, JS Kim, J Gómez-Luna, O Mutlu IBM Journal of Research and Development 63 (6), 3: 1-3: 19, 2019 | 118 | 2019 |
| CoNDA: Efficient cache coherence support for near-data accelerators A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, R Ausavarungnirun, ... Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 93 | 2019 |
| GenASM: A high-performance, low-power approximate string matching acceleration framework for genome sequence analysis DS Cali, GS Kalsi, Z Bingöl, C Firtina, L Subramanian, JS Kim, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 90 | 2020 |
| Buddy-RAM: Improving the performance and efficiency of bulk bitwise operations using DRAM V Seshadri, D Lee, T Mullins, H Hassan, A Boroumand, J Kim, MA Kozuch, ... arXiv preprint arXiv:1611.09988, 2016 | 75 | 2016 |
| Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions S Ghose, K Hsieh, A Boroumand, R Ausavarungnirun, O Mutlu arXiv preprint arXiv:1802.00320, 2018 | 73 | 2018 |
| Google neural network models for edge devices: Analyzing and mitigating machine learning inference bottlenecks A Boroumand, S Ghose, B Akin, R Narayanaswami, GF Oliveira, X Ma, ... 2021 30th International Conference on Parallel Architectures and Compilation …, 2021 | 50 | 2021 |
| Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms K Hsieh, S Khan, N Vijaykumar, KK Chang, A Boroumand, S Ghose, ... Evaluation. In ICCD 1, 2, 2016 | 39 | 2016 |
| The processing-in-memory paradigm: Mechanisms to enable adoption S Ghose, K Hsieh, A Boroumand, R Ausavarungnirun, O Mutlu Beyond-CMOS Technologies for Next Generation Computer Design, 133-194, 2019 | 30 | 2019 |
| Polynesia: Enabling effective hybrid transactional/analytical databases with specialized hardware/software co-design A Boroumand, S Ghose, GF Oliveira, O Mutlu arXiv preprint arXiv:2103.00798, 2021 | 25 | 2021 |
| Mitigating edge machine learning inference bottlenecks: An empirical study on accelerating Google edge models A Boroumand, S Ghose, B Akin, R Narayanaswami, GF Oliveira, X Ma, ... arXiv preprint arXiv:2103.00768, 2021 | 22 | 2021 |
| LazyPIM: Efficient support for cache coherence in processing-in-memory architectures A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, N Hajinazar, ... arXiv preprint arXiv:1706.03162, 2017 | 19 | 2017 |
| Practical Mechanisms for Reducing Processor–Memory Data Movement in Modern Workloads A Boroumand Carnegie Mellon University, 2020 | 17 | 2020 |
| Using ECC DRAM to adaptively increase memory capacity Y Luo, S Ghose, T Li, S Govindan, B Sharma, B Kelly, A Boroumand, ... arXiv preprint arXiv:1706.08870, 2017 | 11 | 2017 |
| Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design A Boroumand, S Ghose, GF Oliveira, O Mutlu 2022 IEEE 38th International Conference on Data Engineering (ICDE), 2997-3011, 2022 | 7 | 2022 |
Onur MutluETH Zürich and Carnegie Mellon UniversityEmail verificata su inf.ethz.ch
