| Pulse-position and pulse-amplitude modulation interface for serial data link applications W Madany, M Rashdan, ES Hasaneen 2016 Fourth International Japan-Egypt Conference on Electronics …, 2016 | 7 | 2016 |
| A 6.5-to-8GHz cascaded dual-fractional-N digital PLL achieving-63.7 dBc fractional spurs with 50MHz reference D Xu, Y Zhang, H Huang, Z Sun, B Liu, AA Fadila, J Qiu, Z Liu, W Wang, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| An enhanced pam with ppm modulation interface for memory applications W Madany, M Rashdan, ES Hasaneen MJET 37 (2018), 110-122, 2018 | 4 | 2018 |
| A 32kHz-reference 2.4 GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration J Qiu, W Wang, Z Sun, B Liu, Y Zhang, D Xu, H Huang, AA Fadila, Z Liu, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 80-82, 2023 | 2 | 2023 |
| Serial data link interface for memory applications W Madany, M Rashdan, ES Hasaneen 2016 IEEE 59th International Midwest Symposium on Circuits and Systems …, 2016 | 2 | 2016 |
| A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter Y Zhang, Z Sun, B Liu, J Qiu, D Xu, Y Zhang, X Fu, D You, H Huang, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| Adaptive timing correction technique for pulse-amplitude and pulse-position modulation interface W Madany, M Rashdan, ES Hasaneen International Journal of Electronics 106 (12), 1978-1998, 2019 | 1 | 2019 |
| 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1 dBc Fractional Spur and 143.7 fs Integrated Jitter D Xu, Z Liu, Y Kuai, H Huang, Y Zhang, Z Sun, B Liu, W Wang, Y Xiong, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 192-194, 2024 | | 2024 |
| A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range H Huáng, B Liu, Z Liu, D Xu, Y Zhang, W Madany, J Qiu, Z Sun, AA Fadila, ... IEEE Solid-State Circuits Letters, 2024 | | 2024 |
| A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter Y Zhang, Z Sun, B Liu, J Qiu, D Xu, Y Zhang, X Fu, D You, H Huang, ... IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path W Madany, Y Zhang, AA Fadila, H Huang, J Qiu, A Shirane, K Okada ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023 | | 2023 |
| Enhanced Amplitude-Modulation Techniques for Time-Based Serial Data Link Architectures, Master Thesis W Madany Aswan University, 2017 | | 2017 |
| Time-based recovery technique for pulse-position and pulse-amplitude modulation interface W Madany, M Rashdan, ES Hasaneen 2016 28th International Conference on Microelectronics (ICM), 277-280, 2016 | | 2016 |
El-Sayed HasaneenAswan UniversityVerified email at aswu.edu.eg
