| A novel static d-flip-flop topology for low swing clocking M Rathore, W Liu, E Salman, C Sitik, B Taskin Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015 | 9 | 2015 |
| Error probability models for voltage-scaled multiply-accumulate units M Rathore, P Milder, E Salman IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (7 …, 2020 | 8 | 2020 |
| Error probability models to facilitate approximate computing in TFET based circuits M Rathore, E Salman 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 2 | 2018 |
| Precision and Performance-Aware Voltage Scaling in DNN Accelerators M Rathore, P Milder, E Salman Proceedings of the Great Lakes Symposium on VLSI 2023, 237-242, 2023 | | 2023 |
| Exploring the Accuracy vs Energy Efficiency Trade-Offs in Error-Aware Low Voltage Dnn Accelerators M Rathore State University of New York at Stony Brook, 2021 | | 2021 |
| Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks M Rathore State University of New York at Stony Brook, 2014 | | 2014 |
Emre SalmanProfessor of Electrical and Computer Engineering, Stony Brook UniversityEmail verificata su stonybrook.edu
