Dongkook Park
Dongkook Park
Verified email at us.ibm.com
Title
Cited by
Cited by
Year
ViChaR: A dynamic virtual channel regulator for network-on-chip routers
CA Nicopoulos, D Park, J Kim, N Vijaykrishnan, MS Yousif, CR Das
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
3662006
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
J Kim, C Nicopoulos, D Park, R Das, Y Xie, V Narayanan, MS Yousif, ...
Proceedings of the 34th annual international symposium on Computer …, 2007
3292007
A low latency router supporting adaptivity for on-chip interconnects
J Kim, D Park, T Theocharides, N Vijaykrishnan, CR Das
Proceedings. 42nd Design Automation Conference, 2005., 559-564, 2005
3102005
Exploring fault-tolerant network-on-chip architectures
D Park, C Nicopoulos, J Kim, N Vijaykrishnan, CR Das
International Conference on Dependable Systems and Networks (DSN'06), 93-104, 2006
2912006
A gracefully degrading and energy-efficient modular router architecture for on-chip networks
J Kim, C Nicopoulos, D Park, V Narayanan, MS Yousif, CR Das
ACM SIGARCH Computer Architecture News 34 (2), 4-15, 2006
2782006
MIRA: A multi-layered on-chip interconnect router architecture
D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das
2008 International Symposium on Computer Architecture, 251-261, 2008
2772008
Design and analysis of an NoC architecture from performance, reliability and energy perspective
J Kim, D Park, C Nicopoulos, N Vijaykrishnan, CR Das
2005 Symposium on Architectures for Networking and Communications Systems …, 2005
1422005
Performance and power optimization through data compression in network-on-chip architectures
R Das, AK Mishra, C Nicopoulos, D Park, V Narayanan, R Iyer, MS Yousif, ...
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
1082008
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks
TD Richardson, C Nicopoulos, D Park, V Narayanan, Y Xie, C Das, ...
19th International Conference on VLSI Design held jointly with 5th …, 2006
1062006
Reetuparna Das, Yuan Xie, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures
J Kim, C Nicopoulos, D Park
Proceedings of the 34th annual international symposium on Computer architecture, 2007
832007
On the effects of process variation in network-on-chip architectures
C Nicopoulos, S Srinivasan, A Yanamandra, D Park, V Narayanan, ...
IEEE Transactions on Dependable and Secure Computing 7 (3), 240-254, 2008
672008
Design of a dynamic priority-based fast path architecture for on-chip interconnects
D Park, R Das, C Nicopoulos, J Kim, N Vijaykrishnan, R Iyer, CR Das
15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007), 15-20, 2007
592007
A distributed multi-point network interface for low-latency, deadlock-free on-chip interconnects
D Park, C Nicopoulos, J Kim, N Vijaykrishnan, CR Das
2006 1st International Conference on Nano-Networks and Workshops, 1-6, 2006
212006
FLEXIBLE AND ADAPTIVE ON-CHIP INTERCONNECT FOR TERA-SCALE ARCHITECTURES.
M Azimi, D Dai, A Kumar, A Mejia, D Park, R Saharoy, AS Vaidya
Intel Technology Journal 13 (4), 2009
162009
Modular decoupled crossbar for on-chip router
D Park, A Vaidya, A Kumar, M Azimi
US Patent 9,674,114, 2017
142017
MoDe-X: microarchitecture of a layout-aware modular decoupled crossbar for on-chip interconnects
D Park, A Vaidya, A Kumar, M Azimi
IEEE transactions on computers 63 (3), 622-636, 2012
82012
Reduced wake up delay for on-die routers
D Park, A Kumar, D Dai
US Patent 9,250,679, 2016
22016
Reduced wake up delay for on-die routers
D Park, A Kumar, D Dai
US Patent 9,250,679, 2016
22016
FPGA-based prototyping of A 2D mesh/torus on-chip interconnect
D Dai, A Vaidya, R Saharoy, S Park, D Park, HL Thantry, R Plate, E Maas, ...
Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010
22010
Performance enhancement through early release and buffer optimization in network-on-chip router architectures
J Kim, D Park, CA Nicopoulos, N Vijaykrishnan, CR Das
22006
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