| Assertion checkers in verification, silicon debug and in-field diagnosis M Boule, JS Chenard, Z Zilic 8th International Symposium on Quality Electronic Design (ISQED'07), 613-620, 2007 | 326 | 2007 |
| Adding debug enhancements to assertion checkers for hardware emulation and silicon debug M Boulé, JS Chenard, Z Zilic 2006 International Conference on Computer Design, 294-299, 2006 | 289 | 2006 |
| Generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring M Boulé, Z Zilic Springer, 2008 | 133 | 2008 |
| Automata-based assertion-checker synthesis of PSL properties M Boulé, Z Zilic ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008 | 129 | 2008 |
| Incorporating efficient assertion checkers into hardware emulation M Boulé, Z Zilic Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005 | 97 | 2005 |
| Efficient automata-based assertion-checker synthesis of PSL properties M Boulé, Z Zilic 2006 IEEE International High Level Design Validation and Test Workshop, 69-76, 2006 | 82 | 2006 |
| Automata unit, a tool for designing checker circuitry and a method of manufacturing hardware circuitry incorporating checker circuitry Z Zilic, M Boulé US Patent 8,024,691, 2011 | 70 | 2011 |
| Efficient automata-based assertion-checker synthesis of SEREs for hardware emulation M Boulé, Z Zilic 2007 Asia and South Pacific Design Automation Conference, 324-329, 2007 | 49 | 2007 |
| Debug enhancements in assertion-checker generation M Boulé, JS Chenard, Z Zilic IET Computers & Digital Techniques 1 (6), 669-677, 2007 | 42 | 2007 |
| Proving and disproving assertion rewrite rules with automated theorem provers K Morin-Allory, M Boulé, D Borrione, Z Zilic 2008 IEEE International High Level Design Validation and Test Workshop, 56-63, 2008 | 17 | 2008 |
| Defining and providing coverage for assertion-based dynamic verification JG Tong, M Boulé, Z Zilic Journal of Electronic Testing 26, 211-225, 2010 | 16 | 2010 |
| Hardware assertion checkers in on-line detection of faults in a hierarchical-ring network-on-chip JS Chenard, S Bourduas, N Azuelos, M Boule, Z Zilic Workshop on Diagnostic Services in Network-on-Chips, 371-375, 2007 | 16* | 2007 |
| Mygen: Automata-based on-line test generator for assertion-based verification Y Oddos, K Morin-Allory, D Borrione, M Boulé, Z Zilic Proceedings of the 19th ACM Great Lakes symposium on VLSI, 75-80, 2009 | 15 | 2009 |
| Validating assertion language rewrite rules and semantics with automated theorem provers K Morin-Allory, M Boulé, D Borrione, Z Zilic IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 12 | 2010 |
| An FPGA based move generator for the game of chess M Boulé, Z Zilic IEEE Custom Integrated Circuits Conference 2002 Proceedings, 71-74, 2002 | 12 | 2002 |
| Efficient data encoding for improving fault simulation performance on GPUs JG Tong, M Boulé, Z Zilic 2013 International Symposium on Electronic System Design, 138-142, 2013 | 11 | 2013 |
| Airwolf-TG: A test generator for assertion-based dynamic verification JG Tong, M Boulé, Z Zilic 2009 IEEE International High Level Design Validation and Test Workshop, 106-113, 2009 | 11 | 2009 |
| Test compaction techniques for assertion-based test generation JG Tong, M Boulé, Z Zilic ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (1 …, 2013 | 10 | 2013 |
| Assertion clustering for compacted test sequence generation JG Tong, M Boule, Z Zilic Quality Electronic Design (ISQED), 2012 13th International Symposium on, 694-701, 2012 | 10 | 2012 |
| Physique des ondes A St-Amand, M Boulé Presses de l'Université du Québec, 2016 | 7* | 2016 |
