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Bon Woong Ku
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Compact-2D: A physical design methodology to build commercial-quality face-to-face-bonded 3D ICs
BW Ku, K Chang, SK Lim
Proceedings of the 2018 International Symposium on Physical Design, 90-97, 2018
372018
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
362017
Shortest path and neighborhood subgraph extraction on a spiking memristive neuromorphic implementation
CD Schuman, K Hamilton, T Mintz, MM Adnan, BW Ku, SK Lim, GS Rose
Proceedings of the 7th Annual Neuro-inspired Computational Elements Workshop …, 2019
222019
Physical design solutions to tackle FEOL/BEOL degradation in gate-level monolithic 3D ICs
BW Ku, P Debacker, D Milojevic, P Raghavan, D Verkest, A Thean, ...
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
202016
Monolithic 3D IC design: Power, performance, and area impact at 7nm
K Acharya, K Chang, BW Ku, S Panth, S Sinha, B Cline, G Yeric, SK Lim
2016 17th International Symposium on Quality Electronic Design (ISQED), 41-48, 2016
132016
Compact-2D: A physical design methodology to build two-tier gate-level 3-D ICs
BW Ku, K Chang, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
122019
A twin memristor synapse for spike timing dependent learning in neuromorphic systems
MM Adnan, S Sayyaparaju, GS Rose, CD Schuman, BW Ku, SK Lim
2018 31st IEEE International System-on-Chip Conference (SOCC), 37-42, 2018
122018
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM
Y Peng, BW Ku, Y Park, KI Park, SJ Jang, JS Choi, SK Lim
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
122015
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?
BW Ku, P Debacker, D Milojevic, P Raghavan, SK Lim
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2016
112016
Built-in self-test for inter-layer vias in monolithic 3D ICs
A Chaudhuri, S Banerjee, H Park, BW Ku, K Chakrabarty, SK Lim
2019 IEEE European Test Symposium (ETS), 1-6, 2019
92019
Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor
BW Ku, Y Liu, Y Jin, S Samal, P Li, SK Lim
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
92018
RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs
H Park, K Chang, BW Ku, J Kim, E Lee, D Kim, A Chaudhuri, S Banerjee, ...
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-4, 2019
82019
Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs
H Park, BW Ku, K Chang, DE Shim, SK Lim
Proceedings of the 2020 International Symposium on Physical Design, 47-54, 2020
72020
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity
BW Ku, T Song, A Nieuwoudt, SK Lim
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
72017
Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library
K Chang, BW Ku, S Sinha, SK Lim
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD …, 2017
62017
Simulating and estimating the behavior of a neuromorphic co-processor
CD Schuman, R Pooser, T Mintz, MM Adnan, GS Rose, BW Ku, SK Lim
Proceedings of the Second International Workshop on Post Moores Era …, 2017
52017
ML-based wire rc prediction in monolithic 3d ics with an application to full-chip optimization
SSK Pentapati, BW Ku, SK Lim
Proceedings of the 2021 International Symposium on Physical Design, 75-82, 2021
22021
Pin-in-the-middle: An efficient block pin assignment methodology for block-level monolithic 3d ics
BW Ku, SK Lim
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020
22020
Evaluating online-learning in memristive neuromorphic circuits
A Wyer, MM Adnan, BW Ku, SK Lim, CD Schuman, RC Pooser, GS Rose
Proceedings of the Neuromorphic Computing Symposium, 1-8, 2017
22017
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs
A Chaudhuri, S Banerjee, J Kim, H Park, BW Ku, S Kannan, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-37, 2021
12021
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